It is often desired in an integrated circuit to delay a signal. In the context of a periodic signal like a clock signal, adjustment of delay can be understood as an adjustment of the phase of the signal. Such phase shifting of a clock signal can be achieved by use of a delay locked loop (DLL), which is commonly used to generate internal clock signals for an integrated circuit from a master external clock signal. Because of the complexity of modern-day integrated circuits, the ability to finely shift the phase of a clock signal is particularly important to ensure proper timing and synchronization within the circuit.
A typical DLL 10 is shown in FIG. 1. As shown, the DLL 10 derives an (internal) output clock signal (ClkOut) (or more than one output clock signal; only one is shown for simplicity) from an (external) input clock signal (ClkIn), in which the phase or delay between the two clocks can be tightly controlled. The DLL 10 comprises a variable delay line (VDL) 12 for providing a variable amount of delay to the input clock signal, and a delay model 14 for providing a fixed delay to the input clock signal. As is known, the delay model 14 models delays outside of the loop, such as those provided by the input buffers, the output buffers, the clock distribution network, etc. (not shown for simplicity). The output of the delay model 14 and the input clock signal, ClkIn, are compared at a phase detector (PD) 16, which essentially determines whether one of these signals is lagging or leading the other, and seeks to bring these two phases into alignment. For example, if the output of the delay model 14 leads ClkIn, then the phase detector 16 outputs an “Up” signal, which increases the delay through the VDL 12. By contrast, if the output of the delay module 14 lags ClkIn, then the phase detector 16 outputs a “Down” signal to decrease the delay through the VDL 12. Through this scheme, the output clock signal, ClkOut, can eventually be locked into a phase relationship with the input clock signal, ClkIn.
One example of a variable delay line (VDL 12) is shown in FIG. 2. As mentioned above, the VDL 12 receives control signals “Up” or “Down” from the phase detector 16 to control the amount of delay that VDL 12 imparts to the input clock signal, ClkIn. In this regard, the exemplary VDL 12 is comprised of a plurality of stages 201 to 204. Four such stages 20 are shown in FIG. 2 for simplicity, but a realistic VDL 12 would normally have a hundred or so stages. Each stage 20 in this example comprises a D flip flop 22 and a few NAND gates 24. The control signals “Up” and “Down” from the phase detector 16 adjust at which stage 20 the ClkIn signal will enter the VDL 12, which in turn defines the delay the VDL 12 imparts. For example, as shown, the “Up”/“Down” control signals have been used to set stage 202 as the entry point for ClkIn. Accordingly, the outputs Q/Q* of flip flop 222 have been set to 1/0, while all other flip flops 224, 223, and 221, have their outputs set to 0/1. As these logic signals percolate through the NAND gates 24 as shown, it can be seen that ClkIn will pass through the NAND gates 24 only in entry stage 202 and all subsequent stages (i.e., 201), and the inherent delays in those NAND gates 24 will function to delay the signal.
Should the phase detector 16 determine that the delay needs adjustment, one of control signals “Up” or “Down” would be asserted. For example, assume from the initial condition in FIG. 2 that an “Up” signal is subsequently asserted, because the phase detector 16 has decided that further delay is warranted in the VDL 12. This would shift the asserted flip flop 22 output Q/Q* of 1/0 to the next stage to the left, i.e., to flip flop 223, with all other flip flop outputs set to 0/1. As a result, the ClkIn signal would now enter the VDL 12 at stage 203, and hence would pass through the NAND gates 24 in stages 203, 202, and 201, thus increasing the delay through the VDL 12. By contrast, a “Down” signal would shift the entry point one stage 20 to the right, decreasing the delay through the VDL 12. In other embodiments, the control signals “Up” and “Down” could be combined for example, and thus only one control signal is necessary to control the VDL 12 in many useful embodiments, although two digital control signals are shown in FIG. 2.
It is typical to provide the circuit elements in the VDL 12 (the flip flops 22, the NAND gates 24, etc.) with a dedicated power supply voltage (VccVDL) which is isolated from the master power supply voltage (Vcc) of the integrated circuit, as is shown in the block diagram of FIG. 1. Providing an isolated power supply to the VDL 12 is beneficial to prevent perturbations in the master power supply Vcc from being seen by the VDL 12 and adversely affecting its delay. Such isolation is important: without isolation, if the VccVDL node becomes higher than normal because of perturbations present on Vcc, delay through the VDL 12 will be quicker than expected, because a higher power supply voltage will cause the circuit elements in the VDL 12 to act more quickly. Conversely, if the VccVDL node becomes lower than normal, the opposite occurs, and delay through the VDL 12 will be slower than expected.
To isolate these two power supplies, and as shown in FIG. 1, VccVDL is generated from the master power supply Vcc using a voltage regulator circuit 15. The details of such a regulator circuit 15 are variant and well known, and hence are not shown for simplicity. While VccVDL is shown as comprising an isolated power supply dedicated only to the VDL circuitry, one skilled in the art will realize that this isolated power supply may be used to power other subcircuits in the integrated circuit as well, depending on the designer's preferences and subject to the noise tolerance of the VDL 12.
One skilled in the art will understand that it is generally desired that the VDL circuitry be as stable and flexible as possible. For example, it is generally not desirable that the delay imposed by the VDL 12 vary with process, voltage, or temperature (“PVT variations”). It is also desirable for design flexibility that the VDL be able to impose a delay over a long time period, as this allows the VDL to be used in integrated circuits having a wide range of clock frequencies. For example, if the VDL 12 can impose a maximum delay t(max) of 10 ns, then such a VDL 12 can be used in devices having a clock frequency of 100 MHz (1/t(max)) or greater. However, at the same time, it is preferred that the delay imposed by the VDL 12 be controllable with a fine resolution.
It has been proposed to control the delay through the VDL through modifying its power supply voltage, VccVDL, as a function of temperature. In U.S. patent application Ser. No. 11/351,037, filed Feb. 8, 2006, which is incorporated herein by reference in its entirety, circuitry is disclosed for sensing the temperature of the integrated circuit proximate to the DLL, and to modify VccVDL accordingly to compensate for any variations the temperature might have on the speed of the delay imposed by the VDL. Thus, if the temperature as sensed is relatively high, suggesting that the VDL would not work as efficiently and hence relatively slowly, VccVDL is increased to increase the speed of the delay through the VDL, thus compensating for the temperature. Likewise, if the temperature as sensed is relatively low, the VccVDL can be decreased accordingly. Of course, this approach merely attempts to remove temperature dependency from the VDL by compensating for temperature-dependently delay using the power supply for the VDL, VccVDL, and does not otherwise disclose means for modifying or controlling the delay over a given operational range of frequencies.
Another approach pertaining more directly to control of the delay of the VDL is disclosed in U.S. patent application Ser. No. 11/132,502, filed May 19, 2005, which is incorporated herein by reference in its entirety. In that application, and as illustrated in FIG. 3, the delays in the stages 20 of the VDL 12 are graduated. Thus, as shown, the stages 20 towards the right of the delay line (201 through 2010) impart a minimum delay (t1) to the input clock signal, ClkIn. By contrast, as one moves towards the left, the delay in each stage gradually increases, e.g., to t2 for stages 2011 and 2012, to t3 for stage 2013, and so on until the highest (coarsest) delay tn is experienced in stages 20n−1 to 20n, As explained in the '502 application, graduating the delay in the stages in this manner allows the VDL 12 to be used over a wider range of frequencies, such that adjustment in the total delay of the VDL 12 is sensibly finer at higher frequencies (where smaller delays are warranted and hence where the entry point tends towards the right end of the delay line) and coarser at lower frequencies (where longer delays are warranted and hence where the entry point tends toward the left end of the delay line). The technique of the '502 application allows for a fine resolution and fine timing control but without the need for an excessive number of stages 20, which reduces layout space and power consumption in the VDL. As further explained in the '502 application, the timing delay tx in each of the stages 20 can be affected for example by varying the lengths or widths of the transistors in the delay elements (e.g., the NAND gates) in each of the stages. Typical values for the delays in each stage would range from approximately 150 ps for the finest stages (t1) to approximately 500 ps for the coarsest stages (tn).
As also shown in FIG. 3, and as discussed in the '502 application, it is advisable to have a portion of the VDL 12 (i.e., some number of stages 20) act as a “buffer.” The buffer stages essentially allow the delay imparted by the VDL 12 to be lessened from an otherwise normal minimum VDL delay as set by an initial entry point. Thus, during conditions in which the DLL seeks to achieve a lock (e.g., upon initialization of the device; exit from a power down mode, etc.), the phase detector 16 will initially set the default entry point into the VDL at the dividing line between the buffer stages and the normal operating stages. This initial entry point is chosen such that it would normally be expected that the delay will need to be increased to achieve a lock, such that the entry point upon lock would fall in the normal operating stages of the VDL 12. However, because of PVT or other variations, it may be the case that achieving a lock will require that the delay through the VDL be lessened, such that the entry point will need to move to the right and into the buffer stages of the VDL 12. Understanding this illustrates the need for a buffer, because if the initial entry point is set at the far right edge of the VDL, the VDL will not be able to produce a smaller delay should one be warranted.
The need for a buffer is unfortunate, because this requires additional stages, and adds to the already large layout of the VDL, which again usually has one hundred or so stages. Moreover, while the approach of the '502 application allows for a single DLL design to be used with a wider range of frequencies, that wider range of frequencies can necessitate a need for a larger number of stages in the buffer, which is undesirable and which might mean that a large number of buffer stages would probably never be used in a real application. For example, a device with a clock cycle of X might require a total buffer delay of Y and a resolution of Z, while a device with a clock cycle of 2X would only require a total buffer delay of 0.5Y and a resolution of 0.5Z; meeting the needs of both of these devices requires a total buffer delay of Y with a resolution of 0.5Z, which doubles the amount of buffer stages required. Moreover, the approach of the '502 patent is sensitive to power supply variation, i.e., to variations in VccVDL. In particular, such power supply sensitivity may again require having an undesirable increase in the number of buffer stages to ensure proper operation during a lower VccVDL condition, or when the VDL is used in devices having naturally lower-voltage power supply requirements. Also, the need for buffer stages increases the forward delay in the DLL, which can complicate the circuitry and is generally not preferred.
A further approach to VDL control is disclosed in S. Kuge et al., “A 0.18-μm 256-Mb DDR SDRAM with Low-Cost Post-Mold Tuning Method for DLL Replica,” IEEE J. Solid State Circuits, Vol. 35, No. 11, pp. 1680-89 (2000) (“Kuge”), which is briefly summarized in FIGS. 4A to 4C. In Kuge, the VDL 31 is controlled to establish a lock using a coarse adjustment mode followed by a fine adjustment mode. As shown in FIG. 4A, to assist in coarse and fine adjustment, Up/Down counter logic 17 is used to assess the output of the phase detector 16, and to create coarse addressing signals (Ac<0.1>) and fine addressing signals (Af<0.2>). (Kuge discusses further addressing signals, but what is summarized and simplified here is sufficient to describe salient aspects of the operation of his technique). These addressing signals are input to Kuge's VDL 31, which is shown in further detail in FIG. 4B. As shown, the VDL 31 comprises a fine adjustment portion and a coarse adjustment portion, which respectively receive the fine addressing signals Af<0.2> and the coarse addressing signals Ac<0.1>. As shown, the fine addressing signals Af<0.2> can create a fine delay by virtue of adding a capacitance (0, C, 2C, 3C, . . . 7C) to the delay line. The coarse addressing signals Ac<0.1> are demultiplexed to produce signals R0 to R3, which set the entry point for the output of the fine adjustment portion, /ClkIn.
Notice as shown in FIG. 4A that the VccVDL regulator 32 receives the Up/Down output from the phase detector 16. This output is used during the coarse adjustment mode to set VccVDL to an optimal level. Specifically, during the coarse adjustment mode, VccVDL is first initialized to a maximum level, and all four coarse stages are used to provide a maximum delay through the coarse adjustment portion, i.e., R0 is high. (None of the fine addressing signals Af<0.2> are asserted during the coarse adjustment mode). Because VccVDL is at a relatively high level, the total delay through the VDL 31 (i.e., through the four coarse stages) is minimized. This initial condition is shown as State 1 of FIG. 4C, which shows the total delay between ClkIn and ClkOut, and thus shows the delay attributable to the delay model 14 (tdelay—model) as well as the delay attributable to the four coarse stages (tcoarse). After this initial condition, VccVDL is incrementally reduced in accordance with the Up/Down control signals from the phase detector 16. As a result of the VccVDL reduction, the delay attributable to the coarse stages is increased as shown in States 2, 3, and 4 of FIG. 4C. The goal of this strategy (of decreasing VccVDL) is to search of an optimal condition in which the total delay exceeds the clock cycle time (tcycle) by an appreciable margin. Such optimal condition is shown in State 4. Note that during this coarse adjustment mode, the entry point into the VDL 31 remains unchanged.
After reaching the optimal coarse adjustment condition (e.g., State 4), the fine adjustment mode is entered. During the fine adjustment mode, VccVDL is kept to the same value that was deemed optimal during the last iteration of the coarse adjustment mode (i.e., at State 4). However, the coarse addressing signals are now modified to bring the number of coarse stages under the tcycle limit; as shown this amounts to removing two of the four coarse stages, which occurs through assertion of signal R2. Because VccVDL is not changed during the fine adjustment mode, the delay imparted by the coarse stages (tcoarse) does not change. However, during the fine adjustment mode, the fine addressing signals Af<0.2> are manipulated to gradually insert fine delays into the VDL (Stages 5, 6, and 7) until a lock condition is met.
Kuge's approach is workable, and in some respects is better than the approach of the '502 application, particularly as concerns layout of the VDL. As can be appreciated, because VccVDL modification is used in addition to a staged approach to adjust the delay during the coarse adjustment mode, the number of coarse stages used can be small. However, any saving in layout of the VDL achieved by Kuge's technique are offset by the additional control complexity that his technique requires. Specifically, his “two mode” approach is difficult to encode in silicon, and such encoding takes up space in its own right. Moreover, switching from one mode to another can create instabilities during the lock process. Simply put, Kuge's approach is difficult to implement and has the potential to suffer from reliability problems.
The art would be benefited by an improved VDL and DLL architecture, and this disclosure provides such a solution.